ics671-05 mds 671-05 f 1 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com 3.3 v olt z ero d elay , l ow s kew b uffer description the ics671-05 is a low phase noise, high-speed pll based, 8-output, low skew zero delay buffer. based on ics? proprietary low jitter phase-locked loop (pll) techniques, the device provides eight low skew outputs at speeds up to 133 mhz at 3.3 v. the outputs can be generated from the pll (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. for normal operation as a zero delay buffer, any output clock is tied to the fbin pin. ics manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world. features ? clock outputs from 10 to 133 mhz ? zero input-output delay ? eight low skew (<200 ps) outputs ? device-to-device skew <700 ps ? low jitter (<200 ps) ? full cmos outputs with 25ma output drive capability at ttl levels ? 5v tolerant fbin and clkin pins ? tri-state mode for board-level testing ? advanced, low power, sub-micron cmos process ? operating voltage of 3.3v ? industrial temperature range available ? packaged in 16-pin soic and tssop packages block diagram clka4 clkb1 clka3 clkb2 clkb3 clka2 clka1 clkb4 control logic s2, s1 clkin fbin 2 vdd 2 gnd 2 1 0 clock synthesis pll feedback is shown from clkb4 for illustration, but may not come from any output
3.3 v olt z ero d elay , l ow s kew b uffer mds 671-05 f 2 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics671-05 pin assignment output clock mode select table note 1. outputs are in high impedence state note 2: buffer mode only; not zero delay between input and output. pin descriptions 12 1 11 2 10 clkin fbin 3 9 clka1 4 clka2 clka4 5 vdd 6 clka3 7 gnd 8 clkb1 vdd gnd clkb4 clkb2 clkb3 s2 s1 16 15 14 13 16-pin narrow (150 mil) soic and 16-pin (173 mil) tssop s1 s0 clka1:a4 clkb1:b4 a and b source pll status 0 0 tri-state (note 1) tri-state (note 1) pll off 0 1 running tri-state (note 1) pll on 1 0 running running clkin (note 2) off 1 1 running running pll on pin number pin name pin type pin description 1 clkin input clock input (5 v tolerant). 2-3 clka1:a4 output clock outputs a1:a4. see table above. 4 vdd power power supply. connect to 3.3 v. 5 gnd power connect to ground. 6-7 clkb1:b4 output clock outputs b1:b4. see table above. 8 s2 input select input 2. see table above. internal pull-up. 9 s1 input select input 1. see table above. internal pull-up. 10-11 clkb1:b4 output clock outputs b1:b4. see table above. 12 gnd power connect to ground. 13 vdd power power supply. connect to 3.3 v. 14-15 clka1:a4 output clock outputs a1:a4. see table above. 16 fbin input feedback input. connect to any outp ut under normal operation (5 v tolerant).
3.3 v olt z ero d elay , l ow s kew b uffer mds 671-05 f 3 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics671-05 external components the ics671-05 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01mf should be connected between vdd and gnd on pins 4 and 5, and vdd and gnd on pins 13 and 12, as close to the device as possible. a series termination resistor of 33 w may be used to each clock output pin to reduce reflections. absolute maximum ratings stresses above the ratings listed below can cause per manent damage to the ics671-05. these ratings, which are standard values for ics commercially rated part s, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electr ical parameters are guaranteed on ly over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3 v 10%, ambient temperature -40 to +85 c, unless stated otherwise item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v clkin and fbin inputs -0.5 v to 5.5 v electrostatic discharge 2000 v ambient operating temperature 0 to +70 c industrial temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.6 v input high voltage v ih 2v input low voltage v il 0.8 v input low current i il vin = 0v 50 a input high current i ih vin = vdd 100 a output high voltage v oh i oh = -12 ma 2.4 v ouput low voltage v ol i ol = 12 ma 0.4 v
3.3 v olt z ero d elay , l ow s kew b uffer mds 671-05 f 4 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics671-05 ac electrical characteristics vdd = 3.3 v 10%, ambient temperature -40 to +85 c, c load at clk = 15 pf, unless stated otherwise note 1: with clkin = 100 mhz, fbin to clka4, all outputs at 100 mhz note 2:when there is no clock si gnal present at clkin, the device will enter power-down mode. the pll is stopped and the outputs are tri-state. note 3: withh vdd at a steady rate and valid clocks at clkin and fbin. output high voltage, cmos level v oh i oh = -8 ma vdd-0.4 v operating supply current idd no load, s2 = 1, s1 = 1, note 1 25 ma power down supply current iddpd clkin = 0, s2 = 0, s1 = 1 12 a clkin = 0, note 2 12 a short circuit current i os each output 50 ma input capacitance c in s2, s1, fbin 5 pf parameter symbol conditions min. typ. max. units input clock frequency f in see table on page 2 10 133 mhz output clock frequency see table on page 2 10 133 mhz output rise time t or 0.8 to 2.0v, cl=30 pf 1.5 ns output fall time t of 2.0 to 0.8v, cl=30 pf 1.25 ns output clock duty cycle t dc measured at vdd/2 45 50 55 % device to device skew rising edges at vdd/2, note 3 700 ps output to output skew rising edges at vdd/2, note 3 200 ps input to output skew rising edges at vdd/2, fbin to clka4, s1 = 1, s0 = 1, note 1 250 ps maximum absolute jitter cl = 15 pf, measured at 66.67m 130 ps cycle to cycle jitter cl = 30 pf, measured at 66.67m 200 ps cl = 15 pf, measured at 66.67m 200 cl = 15 pf, measured at 133.33m 100 pll lock time note 3 1.0 ms parameter symbol conditions min. typ. max. units
3.3 v olt z ero d elay , l ow s kew b uffer mds 671-05 f 5 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics671-05 thermal characteristics (16-pin soic) thermal characteristics (16-pin tssop) parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w
3.3 v olt z ero d elay , l ow s kew b uffer mds 671-05 f 6 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics671-05 package outline and package dimensions (16-pin soic, 150 mil. narrow body) package dimensions are kept curr ent with jedec publication no. 95 index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
3.3 v olt z ero d elay , l ow s kew b uffer mds 671-05 f 7 revision 031004 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics671-05 package outline and package dimensions (16-pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information while the information presented herein has been checked for both ac curacy and reliability, integrated circuit systems (ics) ass umes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result f rom its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other appli cations such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recomme nded without additional processing by ics. ics reserves the right to change any circui try or specifications without notice. ics does not aut horize or warrant any ics product for use in life support de vices or critical medical instruments. part / order number marking shipping packaging package temperature ics671m-05i ics671m-05i tubes 16-pin soic -40 to +85 c ics671m-05it ics671m-05i tape and reel 16-pin soic -40 to +85 c ics671g-05i ics671g-05i tubes 16-pin tssop -40 to +85 c ics671g-05it ics671g-05i tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
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